why does ModelSim capture at the same edge

As expected, your code should be capturing all of ep_data in the same clock edge as everything else.

There's no black magic VHDL behaviour there.

Are you running a RTL or gate level simulation?

If it's gate level, there's a (unlikely) possibility it's due to delays.

But I'd wager it's a subtle bug somewhere before that's delaying half of ep_data one more clock -- been there, done that. :)

Are you looking at the actual ep_data and local_data signals in Modelsim?