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Altera_Forum
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12 years ago

Why does infer Quartus so many M10k blocks in this case?

Hi, For a Cyclone-V based designed I have defined a simple dual-ported ram in vhdl, with a data-width of 9-bits, 12-bit address width and 3648 elements (vhdl file attached). Using 9-bit eleme...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Are you actually running out of memory blocks?

It might just be that more blocks are being used in order to make it easier to meet the timings?

(I don't know if such changes can be made that late on though.)