Honored Contributor
Honored ContributorHi David,
Have you tried making the .qip the top level design entity in your project? Because that makes the thing "just work TM" in my case. I just can't figure out why the presence of a ddr controller would make this happen. I'm starting to think this is actually a bug, and unfortunately not the only one I have encountered in the course of getting quartus to work for me. It appears there are some unspecified interactions between components of quartus where one component thinks something different about a project than another. In particular the interaction between qsys / pin planner and assignment editor seems feeble to say the least, and the only way I've been able to get *consistent* results is by editing pin assignments (excluding the ones made through the TCL script) in the pin planner, and that is a chore. If I do it any other way (importing a csv file) I usually get wrong assignments, and I've even had it that some pin assignments showed up twice in the pin planner. So far I've only used a very limited subset of functionality, and most of the cases I get things working after trial and error and by performing steps in a very specific order. This suggests that there is limited software testing at Altera. I would file bug reports, but I wouldn't know where and as there is no public bug reporting system I can't see if my bugs are known issues/features or not. regards, Theo --- Quote Start --- Hello, I am having this exact same problem. I have a project utilizing a Cyclone V 5CEFA2F23C8N. It has a single Micron MT41K128M16 memory. Had an average sized Qsys project put together and compiled successfully. When I would try to do the Quartus build I would get the following error. ************************ Error (17044): Illegal connection found on I/O input buffer primitive poc: poc|poc_mem_if_ddr3_emif_0: mem_if_ddr3_emif_0|poc_mem_if_ddr3_emif_0_p0: p0|poc_mem_if_ddr3_emif_0_p0_acv_hard_memphy: umemphy|poc_mem_if_ddr3_emif_0_p0_acv_hard_io_pads: uio_pads|poc_mem_if_ddr3_emif_0_p0_altdqdqs: dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev: altdq_dqs2_inst|strobe_in. Source IO poc: poc|poc_mem_if_ddr3_emif_0: mem_if_ddr3_emif_0|poc_mem_if_ddr3_emif_0_p0: p0|poc_mem_if_ddr3_emif_0_p0_acv_hard_memphy: umemphy|poc_mem_if_ddr3_emif_0_p0_acv_hard_io_pads: uio_pads|poc_mem_if_ddr3_emif_0_p0_altdqdqs: dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev: altdq_dqs2_inst|obuf_os_0 also drives out to other destination than the buffer. ****************** The above is reformatted to see the instances more clearly. I went ahead and stripped the Qsys project down to nothing more than a clock and the memory... and the top level was just the port definitions and some wires to connect from Qsys instantiation. Still the same error. I've tried both the hard and soft controllers. still the same error... Cyclone V does not support alt_mem_phy, so I couldn't try that one... I've compiled with 13.1, 14.0, & 14.1... Still the same error. I've wiped the database and deleted all of the assignments... Still the same error. Any help would be appreciated. david --- Quote End ---
