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This is not correct. I never use Qsys as the top-level module.
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OK. In that case I would greatly appreciate your input on what I am dong wrong in the workflow pasted below. With the qsys "simple.qip" as top-level entity it works, with the schematic as top-level entity it doesn't.
(maybe I should have been clearer: it's not the actual .qsys file that I used as one of the design files - it was the generated .qip file)
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http://www.alteraforum.com/forum/showthread.php?t=45927 (see Post#2 attachment)
http://www.alteraforum.com/forum/showthread.php?t=43992 (see Post#5 attachment)
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I had actually already picked up on those earlier. Thanks a lot for sharing :-). The settings I used for the ddr3 controller actually came from the readme in one of your examples.
Though my personal experience with tcl is rather limited, I'm certain that I will get the hang of that eventually - I really don't like GUI/IDE's which *hide* how/why things work and often consider such tools harmful in the long run. Having said that, I also have to deal with people who don't know how to make, diff, grep and git clone, and by using GUI tools I can at least get some basics across without having to deal with that too.
regards, Theo
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Below you will find a quite minimalistic work-flow that reproduces the issue. I tried to make things as minimalistic as possible, even removing debugging (shouldn't matter as it is a compile-time problem). The design works "perfectly" (with a simple program in a memory initialization file blinking leds on a bemicro cv) WITHOUT the ddr3 stuff (clicking the "use" checkbox (*) in qsys to disable it) while a block diagram/schematic is the top-level entity. WITH ddr interface compilation fails IF a block diagram/schematic is used as the top level entity. The only "external" component I used as a compromise to my "from scratch" philosophy is a pin assignment csv file, but that should be irrelevant as compilation fails early. Replacing std_logic_vector (0 downto 0) by std_logic as suggested by solution rd05232011_576 (ancient) removes some warnings, but the error remains.
new project
directory: simple_nios_plus_ddr
name: simple
save project
select Cyclone V:5CEFA2F23C8
tools -> qsys
processors and perhipherals -> embedded processor -> NiosII gen 2 processor
Main: select "Nios II/e"
JTAG Debug: deselect "Include JTAG debug"
Vectors: reset vector memory = absolute 0x00000000
exception vector memory = absolute 0x00000020
break vector memory = absolute 0x00000020
-> finish
basic functions -> on-chip memory
total memory size: 8192 bytes
-> finish
processors and perhipherals -> perhipherals -> pio
-> finish
memory interfaces and controllers->memory interfaces with uniphy->ddr3 sdram controller with uniphy
phy settings->speed grade 8
phy settings->enable hard external memory interface = enabled
phy settings->memory clock frequency: 333.3333MHz
phy settings->PLL reference clock frequency: 50 MHz
phy settings->Rate on avalon mm intergace: full
library->MICRON MT41J64M16LA-15E
controller settings->generate power-of-2 data bus widths for qsys or sopc builder = set
diagnostics->debugging feature set: no debugging
->finish
connect clk to nios2_gen2_0:clk, onchip_memory2_0:clk1 and pio_0:clk
connect clk_reset to nios2_gen2_0:reset, onchip_memory2_0:reset1 and pio_0:reset
connect data_master to onchip_memory2_0:s1 and pio_0:s1
connect instruction_master to onchip_memory2_0:s1
connect clk to mem_if_ddr3_emif_0:pll_ref_clk,mp_cmd_clk_0,mp_rfifo_clk_0 and mp_wfifo_clk_0
connect clk_reset to mem_if_ddr3_emif_0:global_reset,soft_reset,mp_cmd_reset,mp_rfifo_reset_n_0 and mp_wfifo_reset_n_0
connect data_master to mem_if_ddr3_emif_0:avl_0
connect instruction_master to mem_if_ddr3_emif_0:avl_0
set mem_if_ddr3_emif_0 avl_0 base address to 0x10000000
export mem_if_ddr3_emif_0:status -> "status"
export pio_0:external_connection -> "leds"
set onchip_memory2_0 base address to 0x0000000
set pio_0 base address to 0x2000
save "simple.qsys"
generate hdl->VHDL (or verilog, that's not relvant)
-> finish
this mentions that a tcl script must be run after analysis but before fitting
now add simple.qip to project
assignments -> import assignments -> "bemicro_cv.csv"
file->new->block diagram/schematic file, save as "toplevel.bdf"
insert->symbol->simple.bsf (the nios system)
insert->symbol->library->primitives->pin->input (clock_input)
insert->symbol->library->primitives->pin->input (reset_input)
insert->symbol->library->primitives->pin->output (led[0..7])
etcetera... connect everything appropriately
save and set toplevel.bsf as top level entry
compilation fails during the analysis & synthesis stage:
Error (17044): Illegal connection found on I/O input buffer primitive simple:inst|simple_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|simple_mem_if_ddr3_emif_0_p0:p0|simple_mem_if_ddr3_emif_0_p0_acv_hard_memphy:umemphy|simple_mem_if_ddr3_emif_0_p0_acv_hard_io_pads:uio_pads|simple_mem_if_ddr3_emif_0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|strobe_in. Source IO simple:inst|simple_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|simple_mem_if_ddr3_emif_0_p0:p0|simple_mem_if_ddr3_emif_0_p0_acv_hard_memphy:umemphy|simple_mem_if_ddr3_emif_0_p0_acv_hard_io_pads:uio_pads|simple_mem_if_ddr3_emif_0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|obuf_os_0 also drives out to other destination than the buffer.
running the aforementioned tcl script (even though analysis failed) doesn't change anything.
After changing the top level entry to simple.qip (instead of toplevel.bsdf) the same project compiles (with some warnings) and the resultant .sof can be uploaded to a bemicro cv (of course with the software included as a memory initialization file as jtag debugging doesn't work because the relevant bits have been removed)
(*) there seems to be an unrelated bug in qsys where clicking the "use" checkbox next to a component again to "use" it again after having disabled it, will show the component *with* any bus/clock/reset etc connections connected, but qsys will complain that these lines are actually unconnected. This can be "solved" by clicking every connection to first disconnect, and then clicking it again to reconnect it.
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