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Altera_Forum's avatar
Altera_Forum
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18 years ago

Why can't find timing report of clk output from PLL module?

In my system:

PLL Module:

input: 50MHz

C0 output: 80MHz

C1 output: 100MHz

After full compilation with classic timing analyzer, I can only find timing report of PLL.C0 clk and can't find any infomation about PLL.C1. WHY?

Thanks in advance:)

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    I almost get the answer！

    In SOPC Builder, My custom IP has two clock input.

    CLK0

    CLK1

    I use altpll IP and generate two clock:

    PLL.C0 = 80 MHz

    PLL.C1 = 100MHz

    then I connect PLL.C0 to CLK0; PLL.C1 to CLK1, then generate....

    After full compilation in QuartusII 7.2, I open RTL View and find that

    both CLK0 & CLK1 connected to PLL.C1, and neither connected to PLL.C0.

    That's why I can't find timing report of PLL.C0.

    But Why both CLK0 & CLK1 connected to PLL.C1, and neither connected to PLL.C0?