Why can't find timing report of clk output from PLL module?

I almost get the answer！

In SOPC Builder, My custom IP has two clock input.

CLK0

CLK1

I use altpll IP and generate two clock:

PLL.C0 = 80 MHz

PLL.C1 = 100MHz

then I connect PLL.C0 to CLK0; PLL.C1 to CLK1, then generate....

After full compilation in QuartusII 7.2, I open RTL View and find that

both CLK0 & CLK1 connected to PLL.C1, and neither connected to PLL.C0.

That's why I can't find timing report of PLL.C0.

But Why both CLK0 & CLK1 connected to PLL.C1, and neither connected to PLL.C0?