Why am I getting a syntax error in my case structure?

There are several problems with your code:

1. Latch inference. All signals assigned in the process should be assigned in EVERY BRANCH to avoid infering latches (unless it is a synchronous process). This means assigning '0' or '1'. Assigning 'X' does not map to real hardware

2. Assigning to 'X' is not dont care - it is unknown. You should not be assigning signals to 'X' or checking a signal for 'X' in synthesisable code. You are very likely to get differences in simulated and real behaviour.