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Altera_Forum
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11 years ago

Why am I getting a syntax error in my case structure?

I am building an ALU control unit in VHDL and I have been getting these errors when compiling. Error (10500): VHDL syntax error at alu_control.vhd(43) near text "when"; expecting "end", or "("...
Altera_Forum's avatar
Altera_Forum
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11 years ago

The compiler seems to not like ALUCtrl in the sensitivity list since it is of type out, but without it the compiler infers latches, plus a couple of warnings. 


Warning (10631): VHDL Process Statement warning at alu_control.vhd(20): inferring latch(es) for signal or variable "ALUCtrl", which holds its previous value in one or more paths through the process
Warning: Latch ALUCtrl$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Funct
Warning: Latch ALUCtrl$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Funct
Warning: Latch ALUCtrl$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Funct

All other warnings are simply pin assignment warnings.

Is there any way to avoid these potential errors?