Why am I getting a syntax error in my case structure?

`For clarity (please do this the next time you post code as well)

library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------
entity alu_control is
	port( 
		ALUOp: in std_logic_vector(1 downto 0);
		Funct: in std_logic_vector(5 downto 0);
		ALUCtrl: out std_logic_vector(3 downto 0)
	);
end entity alu_control;
----------------------------------------------------
architecture alu_control_arch of alu_control is
begin
process (ALUOp, Funct, ALUCtrl)
begin
	case ALUOp is
		when "00" =>
			if Funct = "xxxxxx" then
				ALUCtrl <= "0010";
			end if;
		when "01" =>
			if Funct = "xxxxxx" then
			ALUCtrl <= "0110";
			end if;
		when "10" =>
			if Funct = "100000" then
				ALUCtrl <= "0010";
			elsif Funct = "100010" then
				ALUCtrl <= "0110";
			elsif Funct = "100100" then
				ALUCtrl <= "0000";
			elsif Funct = "100101" then
				ALUCtrl <= "0001";
			elsif Funct = "101010" then
				ALUCtrl <= "0111";
			else
				ALUCtr <= "xxxx";
			end if;
		when others =>
			ALUCtrl <= "xxxx";
	end case;
end process;
end architecture alu_control_arch;