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Altera_Forum's avatar
Altera_Forum
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11 years ago

Why am I getting a syntax error in my case structure?

I am building an ALU control unit in VHDL and I have been getting these errors when compiling. Error (10500): VHDL syntax error at alu_control.vhd(43) near text "when"; expecting "end", or "("...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

That is how I have it written in my code for the ALU unit and it worked. THe simulation for it was correct as well.

So not sure why it doesnt work here, but changing it to elseif gives this

Error (10500): VHDL syntax error at alu_control.vhd(32) near text "Funct"; expecting "(", or "'", or "."

This error repeats for every elseif line I have written.