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Altera_Forum
Honored Contributor
Honored ContributorWho wins VERILOG_MACRO.qsf or `define.v?
I have a design which `includes a header file which has `defines for default mode, say:`define ASIC_VERSION 32'h00000001 I have an "override" in my .qsf to specify the FPGA build, say:set_glob...
Altera_ForumHonored Contributor
Honored ContributorDid you modify the definition in the include file to surround it with the `ifndef ... `endif lines?
What is the failure you are seeing?
