while loop iteration error

Hi all again!

library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all; 
 
entity whiler is 
port( clk:in std_logic; 
      reset:in std_logic; 
      outer:out std_logic); 
end whiler; 
 
architecture behavior of whiler is 
begin 
     
    process 
        variable index : integer := 0; 
    begin 
        wait until rising_edge(clk); 
        if (reset = '1') then 
            outer <= '0'; 
        elsif (reset = '0') then 
            while index < 6 loop 
                outer <= '1'; 
                index := index + 1; 
            end loop; 
        end if; 
    end process; 
end behavior;