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ser_out <= sr(6); can go after the end if; (associated rising_edge(clk)) before end process; and not infer a register.
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Then you'd get a missmatch between simulation and synthesis. because the process is only sensitive to the clock, in simulation it would only change on any edge of the clock. Because sr(6) will have only been scheduled for a change on the rising edge, and not actually changed yet, ser_out would only get set to the new sr(6) on the falling edge.
You would have to make the process sensitive to sr(6) too to fix this.
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