Whether the latches in design power-up with a default value 0 ?

Physical registers power up to logic zero in the devices, but you can get a register to effectively power up to a logic one by inserting the sense of the logic (and Quartus can do that for you automatically). Thus the declarations (in verilog) 'reg somereg = 0;' and 'reg someother = 1;' are both legal and the registers will effectively power up to 0/1 respectively.

Latches are built with logic, so they will default to the value you have them assume (ie, can be 0 or 1 or 0/1 (ie, unknown)) depending on how you code the latch.