where is my fault in this code?

when I attempt to simulate the design This warning is displayed:

library IEEE;use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity RAM_1 is
   generic ( M : natural:=8 ); -- depth=2**N
   port( clk  : in  std_logic; -- clock
         cs   : in  std_logic; -- chip select
         rw   : in  std_logic; -- read=0/write=1
         addr : in  integer; -- address
         data : inout std_logic_vector(7 downto 0)); -- data
end entity RAM_1;
architecture RTL of RAM_1 is
   type mem_array is array (0 to M**2-1) of std_logic_vector(7 downto 0);
   signal ram : mem_array:=(    X"06",X"02",X"0A",X"06",X"05",X"03",X"07",X"09", 
                                X"02",X"01",X"00",X"06",X"08",X"0B",X"04",X"0F",
                                X"06",X"02",X"0A",X"06",X"05",X"03",X"07",X"09", 
                                X"02",X"01",X"00",X"06",X"08",X"0B",X"04",X"0F",
                                X"06",X"02",X"0A",X"06",X"05",X"03",X"07",X"09", 
                                X"02",X"01",X"00",X"06",X"08",X"0B",X"04",X"0F",
                                X"06",X"02",X"0A",X"06",X"05",X"03",X"07",X"09", 
                                X"02",X"01",X"00",X"06",X"08",X"0B",X"04",X"0F" ); 
begin
   process
   begin                                                
    wait until ( CLK'event and CLK='1');
      if cs='1' then
         if rw='1' then
            ram(addr) <= data;
         else
            data <= ram(addr);
         end if;
      else
         data <= (others=>'Z');
      end if;
   end process;
end RTL;