"When others" best practice?

Hi,

in theory, there can be a slighly different meaning to each option.

A VHDL "if/elsif" strucuture implies priority. That is, in general, more than one branch may match and the first is used.

The VHDL case statement is parallel: only one branch may match.

But even if your "if/else" structure expressed some non-intentional priority, then the "case" statement should, ideally, lead to the same or less logic. Which is doesn't.

What you're experiencing is, probably some tool limitation, which show up in a somewhat "random" fashion.

There's no advice I can offer, except to do what you just did: try, somewhat randomly, multiple ways to express the same code.

You can also try to use conditional assignments, "select" statements, etc.

And try to see what kind of structures your VHDL is being translated into in the RTL netlist. That sometimes provides an hit of what the tool is doing.