What's wrong with my .mif file

It seems as if I only found half of the solution.

While Analysis & Synthesis works with the solution posted above, Simulation won't work - with nearly the same error as Analysis & Synthesis had before. I set up Modelsim Altera Edition with the native link feature - I wrote my own vhdl testbench and launch it via Tool > Run Simulation Tool > RTL Simulation, which worked fine until now. But now

# ** Fatal: (vsim-7) Failed to open VHDL file "./memoryInit/HRTF_L_real_memory_init.mif" in r mode.
#  No such file or directory. (errno = ENOENT)
#     Time: 0 ps  Iteration: 0  Process: /testbench_ols_fft_fading/dut/HRTF_Manager/HRTF_A_L_real/altsyncram_component/MEMORY File: /home/nt-lab/Software/Altera/modelsim_ase/linuxaloem/../altera/vhdl/src/altera_mf/altera_mf.vhd
#  Fatal error in Process MEMORY at /home/nt-lab/Software/Altera/modelsim_ase/linuxaloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 40268
#  

appears in the Modelsim window and

Error (138003): Can't write incremental compilation assignments.  Quartus Prime Settings File /home/ --PATH TO MY DATA --/Testbench_OLS_FFT_Fading.qsf is unwritable.
Error (140001): Can't write LogicLock assignments.  The Quartus Prime Settings File /home/ --PATH TO MY DATA --/Testbench_OLS_FFT_Fading.qsf is unwritable.
Error (138003): Can't write incremental compilation assignments.  Quartus Prime Settings File /home/ --PATH TO MY DATA --/Testbench_OLS_FFT_Fading.qsf is unwritable.
Error (140001): Can't write LogicLock assignments.  The Quartus Prime Settings File /home/ --PATH TO MY DATA --/Testbench_OLS_FFT_Fading.qsf is unwritable.
Error (113025): Missing syntax END in the Memory Initialization File "HRTF_L_real_memory_init.mif"
Error (113025): Missing syntax END in the Memory Initialization File "HRTF_L_real_memory_init.mif"

in the Quartus Window.

Is this really only an encoding error or something different?