Honored ContributorDo you think there is a difference in functionality between these codes?
always @(posedge clk)
begin
A<=0;
if (sel==0)
A<=in_u;
else
A<=in_v;
endalways @(posedge clk)
begin
if (sel==0)
A<=in_u;
else
A<=in_v;
end
always@(posedgeclk)
A<=0;
Honored ContributorYes. The first one will select between in_u and in_v.
In the second one A will be X when the selected input is 1 (and in synthesis, you'll get a multiple driver error)Honored ContributorBut how come the first one will not get an error since I am also assigning 0 to A initially. For the second case, I am just doing the same thing, but moving the resetting part to another sequential clock process.
Honored ContributorHonored ContributorOkay, so that simply means:
1) Assignment in different 'always' blocks --> they are evaluated in parallel, resulting in multiple driver error 2) Assignment in the same 'always' block --> they are evaluated in sequential, where it will reset initially before going into a MUXHonored ContributorHonored ContributorIll just clarify:
always @(posedge clk)
begin
A<=0;
if (sel==0)
A<=in_u;
else
A<=in_v;
end
always @(posedge clk)
begin
A<=in_v;
if (sel==0)
A<=in_u;
end
I tried both pieces of code on Vivado. Strange enough, they both passed!
Honored ContributorHonored ContributorHonored ContributorWas the project set up correctly? Was A removed?
