What's the Altera Equivalent to the Xilinx STARTUP Primitive GSR/GlobalSetReset?

To answer your main question - there is no Altera equivalent to the GSR primitive.

You should be able to route the clock and a reset signal from the HPS to the FPGA fabric directly. What problem are you having? Export the signals in Qsys and then in the top-level HDL wrapper (I assume) that instantiates your Qsys module and your FPGA module just wire the clock and reset from the Qsys module to the FPGA module.