what is wrong in this VHDL code?

You've already gotten some good responses. In case it wasn't already apparent, you are getting that error because of the statement:

else

Hex_out <=("0000000000000000000000000000000");

This makes your code unsynthesizable. What you are telling Quartus II to do is "when there is a clock transition do this, when there is not a clock transition do that."

The problem being, a clock transition is "true" for an infinitesimally short amount of time. So, what you want to tell Quartus II to do is "after a clock transition, do this." You can do that be removing the 'else' statement. You never want an 'else' or 'elsif' with your if (clk'event).