what is wrong in this VHDL code?

For sure I'm no expert in VHDL and maybe there are more elegant solutions, but the following should work:

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library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity DDS_LUT is

port

(

clk : in std_logic;

--encoder_a : in std_logic;

data_b : in integer range 3185 to 4215 ; --std_logic_vector(12 downto 0);

Hex_out : out std_logic_vector (30 downto 0) --(need output with hexa not bin)

);

end;

architecture arc_DDS_LUT of DDS_LUT is

signal hex_out_internal : std_logic_vector (30 downto 0);

begin

hex_out <= hex_out_internal;

-- or maybe: Hex_out (30 downto 0) <= Hex_out_internal (30 downto 0);

process (clk)

begin

if CLK'EVENT and CLK = '1' then

case data_b is

when 3185=> hex_out_internal <= ("1010101101110111011101110111100");

when 3186=> hex_out_internal <= ("1010101101101001110100000011011");

when 3187=> hex_out_internal <= ("1010101101011100001010001111011");

when 3188=> hex_out_internal <= ("1010101101001110100000011011010");

when 3189=> hex_out_internal <= ("1010101101000000110110100111010");

.... and so on

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Hope this helped :)

Right: sensitivity list should be changed, too.