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Altera_Forum's avatar
Altera_Forum
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18 years ago

what is wrong in this VHDL code?

Hey guys i have this VHDL code but when i compile it i got an error message thx said: Error (10818): Netlist error at DSS_LUT.vhd(21): can't infer register for Hex_out[8] because it does not hold...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Do you want only combinational logic or do you want hex_out to be flip-flops? You've combined the constructs for just combinational logic and logic with flops.

If you want just combinational only, drop the CLK references, and drop the "else hex_out <=("0000000000...000");" fragment

If you want logic followed by flops, change the sensitivity list for the process to be CLK, not data_b, AND drop the else hex_out <=("0000000000...000");" fragment.

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