what is wrong in this VHDL code?

You need to add your clock to the sensitivity list. It should be "process (CLK, data_b)" instead of "process (data_b)".

You should also remove the "else" clause after your case since it will clear your outputs anytime there is a change in the signals specified in the sensitivity list that doesn't correspond to a rising edge of clk. In other words if the input data_b changes then your process is evaluated and the outputs will be cleared.

For style look into two alternative coding details:

(a) You can use the "rising_edge" function which is part of the IEEE std logic library.

(b) You can use Hex notation instead of the binary strings.