Contributor
Super ContributorFirst of, assuming you are familiar with Platform Designer (previously called Qsys), check out this online training:
https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsys3000.html
Then, your questions:
1) Yes, it does. See the Platform Designer user guide (not sure if you're using Standard or Pro so select the appropriate guide):
https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/user-guides.html
2) You just make connections between masters and slaves, and sources and sinks. The tool does the rest. See the user guide for details.
3) Can you clarify your address space question? The address space for a memory-mapped interface is based on the slaves attached to a particular master, which you set up in Platform Designer.
4) The user guide discusses how different interfaces can work with each other. Platform Designer automatically generates translation components in the interconnect to allow interfaces to talk to each other. The disadvantage to this is the added logic to the design which, depending on the design and settings, could affect overall performance and potentially, though rarely, cause timing issues.
5) There are many BFMs available just for this purpose. On the user guides list (https://www.intel.com/content/www/us/en/programmable/documentation/lit-ug.html) search for axi to see the guide for the BFMs.
6) Platform Designer outputs plain HDL code (except for if you are using licensed IP, then it's encrypted) even for Avalon. As far as recommended guidelines, the user guide referenced above is your best source of info.
Hope that helps.
#iwork4intel
ContributorThanks for this answer. I am trying to get access to the training course but is not working yet. I have sent an email to the FPGAtraining@intel.com to fix this.
I assume that this "Mentor Verification IP Altera Edition AMBA AXI3 and AXI4" is the related to the BFMs found inside the Qsys. I have a few more questions based on this:
1. Since this document states AMBA and then AXI3 and AXI4, why are the AMBA buses like APB and AHB missing from this document completely?
2. The Aldec ActiveHDL simulator is missing from the list of supported simulators in the user guide. Who should be contacted to get to the bottom of this?
Out of curiousity, I also intrigued by a few other things:
1. Is Avalon able to provide all the functionality that exists inside AMBA and AXI buses or is it inferior in some way? I would assume so due the more limited application of AMBA.
2. If AMBA or AXI components are used, are they converted into Avalon and then back by the Qsys interconnect?
I shall continue study of the user guides.
