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New Contributor

1 year ago

What is the motivation behind the creation of Data Pattern Generator/Checker Verification IP?

The Intel Quartus Prime Platform Designer contains some verification IP that contains the terms "Pattern Checker" and "Pattern Generator" in their name. These were added quite late into the IP suite ...

Simulation

KennyT_altera

Super Contributor

1 year ago

Sstrel is right, this IP usually is use for simulation purposes.

You may take a look the user guide https://www.intel.com/content/www/us/en/docs/programmable/683609/21-3/data-pattern-generator-and-checker.html

And we also have design example here:

https://community.intel.com/t5/FPGA-Wiki/Cyclone-V-ALTLVDS-Design-Example/ta-p/735385

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What is the motivation behind the creation of Data Pattern Generator/Checker Verification IP?

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