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And do you know can we estimate the power consumption of our design in Quartus II after completed compilation?
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You write a testbench that enables the design as you intend to use it, i.e., with realistic traffic on its I/Os, and realistic processing using internal logic.
You run this testbench in Modelsim and create a Value Change Dump (.vcd) file. Then use Altera's power analysis tool to get a power estimate (I think that's right, its been a while since I've done it).
Depending on the FPGA you are using, you need a machine with a huge amount of memory. For the Stratix II design I was working with, I ended up created designs with 5%, 10%, 20%, 30% of the logic I planned on using in the final design, and then extrapolated to a full FPGA.
For a worst-case power analysis, you can create a Qsys system with blocks of registers that you can enable to toggle their outputs. You can create a block size that is say 5% of a device, and then enable one block for a 5% power load, two blocks for 10%, etc.
Cheers,
Dave
Honored Contributor
