Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

What is mean of timing model in EDA Gate Level Simulation?

When I use ModelSim-Altera to do simulation, I run modelsim from Quartus II using Tool-> Run EDA Simulation Tool -> EDA Gate Level Simulation. Then there are three options： Slow-81.2V 8...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks very much, Dave! I will read the link you give. And do you know can we estimate the power consumption of our design in Quartus II after completed compilation?

Thanks!