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I don't have synthesis error when I use three plls but I have critical warning. And the design does not work as I expect when I did onboard debugging. After I remove one pll to use two, there is still crtical warning, the warning changed from the 3rd pll to 2nd pll. But when I debug the design onboard, the design works well as I expect.
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That sounds like progress! :)
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EP4CE55F chip I used in my design, have 4 plls. And each pll can only generated 3 clocks. But I need 4 different clocks although all of them come from same basic clock. This is why I use 2 plls.
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I see.
These three clocks don't have an integer relationship that you can use to create an enable pulse instead of one of the clocks?
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How can I know the location of PLL I used inside FPGA chip?
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I haven't needed to look, so can't give you exact guidelines. Look in the fitter report. There should be a table in there. The same information will be in the files generated by Quartus You can probably also see it in the technology viewer (GUI).
Cheers,
Dave
Honored Contributor
