--- Quote Start ---
Great! Does that help with the synthesis error?
/QUOTE]
I don't have synthesis error when I use three plls but I have critical warning. And the design does not work as I expect when I did onboard debugging. After I remove one pll to use two, there is still crtical warning, the warning changed from the 3rd pll to 2nd pll. But when I debug the design onboard, the design works well as I expect.
--- Quote Start ---
Why can't these four clocks be generated from a single FPGA? If they are all relative to a common reference, then one PLL should be enough. If you have two different clock sources, and the FPGA needed to use a higher clock frequency phase-locked to the two clock sources, then of course you would need two PLLs.
Cheers,
Dave
--- Quote End ---
EP4CE55F chip I used in my design, have 4 plls. And each pll can only generated 3 clocks. But I need 4 different clocks although all of them come from same basic clock. This is why I use 2 plls.
How can I know the location of PLL I used inside FPGA chip?
Thanks very much.
Honored Contributor
