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Actually I can use two plls instead of three.
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Great! Does that help with the synthesis error?
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In my design, I need to design a control module and it needs to generate several different rate clocks for an custom design image sensor. And the real-time processing is done in FPGA too. I need another pll to generate double rate clock from basic clock to compute histogram. So generally I need at least 4 clocks from PLL. Other slow clocks will be generated through counter.
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Why can't these four clocks be generated from a single FPGA? If they are all relative to a common reference, then one PLL should be enough. If you have two different clock sources, and the FPGA needed to use a higher clock frequency phase-locked to the two clock sources, then of course you would need two PLLs.
Cheers,
Dave
Honored Contributor
