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You should look at the warning message and then review the handbook for the FPGA. Look at the PLLs that Quartus is trying to use, and then confirm that the CLKIN pin available cannot be used by one or more of your PLLs. That way you understand the synthesis error. You may not be able to do anything about the error, but you will know to avoid this problem when designing your own hardware.
The board is just a bunch of headers, you could always supply another clock source.
If the clock frequency is not that high, you could also drive a PLL output to a pin then jumper that pin over to another CLKIN input.
You can also cascade PLLs; use a PLL reference clock that is the output of another PLL on the FPGA. You may get warnings regarding jitter, but if you are just testing ideas, then that may not matter.
And finally, why do you need so many clocks?
Cheers,
Dave
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Thanks for your suggestions, Dave. Actually I can use two plls instead of three. In my design, I need to design a control module and it needs to generate several different rate clocks for an custom design image sensor. And the real-time processing is done in FPGA too. I need another pll to generate double rate clock from basic clock to compute histogram. So generally I need at least 4 clocks from PLL. Other slow clocks will be generated through counter.
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