Forum Discussion

ThomasTessier's avatar
ThomasTessier
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

What is: altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst.tr file and how to use it?

I am running an ArriaV design in simulation (QuartusPrime 21.1 with Cadence Xcelium). An in my simulation directory I get the following file: altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_in...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 years ago

    Hi Tom,


    I can see which file that you are mentioning and it's a file that has been generated when running the simulation. This file actually captures the transaction of the simulation. So the size is depends on the transaction.

    If you want to disable this file, you can check in the testbench file located in the submodules folder.

    The name of the testbench file is altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench.v.

    In the testbench file, you can scroll down until line 694 to 704. These lines will create the file and write the transactions into the file.

    By disabling lines 694 to 704, the file will not generated.


    Regards,

    Adzim


ThomasTessier's avatar
ThomasTessier
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

AdzimZM,

Not being able to disable it is not really acceptable. For my simulation this file is 19MBytes and I haven't even use the DDR3 at this point. In fact my simulation doesn't have a DDR3 simulation model attached to the FPGA design. I was actually planning on replacing the DDR3 Avalon device with the Avalon BFM Slave for simulation so I would have some data to playback.

So is there really no way to disable the creation of this file, I would have expected a Parameter or at a minimum a `define that could do the work?

TomT...