What I did Wrong in my Verilog Project? (Quartus cannot compile it)

As a general remark, your code is rather complex for a "First_Project". I hope, you're able to solve the involved problems without too much frustration. Most people start learning HDL programming with more basic design problems.

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on positive or on negative edges I should send one bit

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I understand now, why you wrote always @(outclock), but unfortunately, it's not synthesizable. You need a kind of DDIO (dual-data-rate) output register. I present a principle solution in the code snippet below (registering two bits and use a multiplexer to select the right output data bit for both clock phases), for high OutClock speeds, explicite instantiation of a DDIO primitive may be required.

The other point is to keep the requirements for RAM inference. I'm showing below a construct that is accepted by the Quartus compiler, but I'm not sure if it's acceptable to register the RAM output 1 clock cycle in advance. If it doesn't work this way, you have to use a different construct, that reserves one clock cycle delay for the RAM read action.

always @(posedge OutClock)
begin
  begin
    {CurShiftData, OutData_n,OutData_p}<=CurShiftData;
  end
  if(CurPos)
  begin 
    CurPos=CurPos-1'b1;
  end
  else
  begin
    CurPos<=79;
    CurShiftData<=EndPos;
    if(EndPos==0 && EndPosSw)
    begin
      EndPosSw<=0;
      CurShiftData<=CurShiftData_s1;
    end
    else
    begin
      EndPosSw<=1;
      EndPos<=EndPos+1'b1;
      CurShiftData<=CurShiftData_s2;
    end
  end
  CurShiftData_s1<=TimeStep];
  CurShiftData_s2<=RingData;
end
assign OutData = (OutClock)?OutData_p:OutData_n;