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Altera_Forum
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15 years ago

What I did Wrong in my Verilog Project? (Quartus cannot compile it)

Hi, I am trying to implement data conversion algorithm. It has 8 inputs and its clock running at 400MHz and 1 bit output and its clock running at about 1MHz. During the project I need to f...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Dear FvM,

thank you for your reply. Actually, I really cannot guess what to do, I am new in FPGA... I need to implement the following algorithm:

on posetive or on negative edges I should send one bit from 80 bit array CurShiftdata;

if there is no data available on CurShiftData, I need to generate CurShiftData according to the following rules:

[79:75] are zeros,

[76:64] bits corresponds to EndPos, (I am using [79:64]<=EndPos am I right?)

the rest [63:0] 64 bit data are collected 1/1024 times from TimeStep array, and on other cases from RingData.

Actually, I have no filling what your comment about RAM output register means. Yes, I understand that it is shift register, and probably it is by some means also RAM, but when it is RAM or not, I cannot define myself, so I cannot figure out how to fix this problem. Please, help me!

Sincerely,

Ilghiz