What I did Wrong in my Verilog Project? (Quartus cannot compile it)

Dear FvM,

thank you for your kind suggestions. I tried to rewrite everything according to your suggestions and got my project compiled, however I am still not sure that everything is ok.

I got very impressive Fmax counts for several clocks of my design: 438MHz for InReady and 153MHz for the internal clock which is 4 times demux of InReady, so, I need at least 100MHz. Indeed I have two designs, one is running with InReady clocked at 200MHz and one other slightly differ with more wider reg [27:0] InData running at 400MHz clock.

What I cannot understand right now in my Quartus compilation, is the following: I allocate reg [63:0] RingData [0:8191], so, it is 512KBits, however, in "Flow Summary" I used zero bits.

Would enybody comment me where my RingData and TimeStep arrays was allocated? In RTL it is marked as sync_ram, but if the internal Cyclone 3 memory of 608K were used, why the Flow Summary has zero bits of usage.

I am attaching complete code of this project, RTL, Fmax and Flow summaries.

Sincerely,

Ilghiz

module My_First_Project (InData, InReady, OutClock, OutData);
parameter MaxK=8;
parameter BLKSIZE=1024;
parameter MaxN=MaxK*BLKSIZE;
input   InData;
input  InReady, OutClock;
output OutData;
reg    OutData;
reg signed  LD0, LD1, LD2, LD3, LD4;
reg signed  PE, NE;
reg  DeMuxCounter;
reg  H00, H01, H02, H03, H04, H05, H06, H07, H08, H09;
reg  H10, H11, H12, H13, H14, H15, H16, H17, H18, H19;
reg  H20, H21, H22, H23, H24, H25, H26, H27, H28, H29;
reg  H30, H31, H32, H33, H34, H35, H36, H37, H38, H39;
reg  SumS1, SumS2;
reg  LevelS1, LevelS2;
reg signed  x1, x2, x3, x4;
reg  y1, y2, y3, y4, yy1, yy2, yyy, LS1, LS2;
reg  z1, z2, z3, z4, zz1, zz2, zzz;
reg  NadoT;
reg  CurTime;
reg  RingData ;
reg  TimeStep ;
reg  BeginPos;
reg  EndPos;
reg  CurShiftData;
reg   CurPos;
reg        EndPosSw;
initial
begin
  LD4<=0;
  CurTime=0;
  SumS1=1;
  SumS2=1;
  LevelS1=1;
  LevelS2=1;
  NadoT=0;
  DeMuxCounter=0;
  BeginPos=0;
  EndPos=0;
  CurPos=79;
  EndPosSw=1;
end
always @(posedge InReady)
begin
  PE <= {PE, InData};
end
always @(negedge InReady)
begin
  NE <= {NE, InData};
  DeMuxCounter<=DeMuxCounter+1'b1;
end
always @(posedge DeMuxCounter)
begin
  if(NadoT)
  begin
    RingData=H39;
    NadoT=NadoT-1'b1;
    if(BeginPos==0) TimeStep]=CurTime;
    BeginPos=BeginPos+1'b1;
  end
  begin
    LD0<=LD4;
    LD1<={PE, NE, PE, NE, PE, NE, PE, NE,
          PE, NE, PE, NE, PE, NE, PE, NE};
    LD2<={PE, NE, PE, NE, PE, NE, PE, NE,
          PE, NE, PE, NE, PE, NE, PE, NE};
    LD3<={PE, NE, PE, NE, PE, NE, PE, NE,
          PE, NE, PE, NE, PE, NE, PE, NE};
    LD4<={PE, NE, PE, NE, PE, NE, PE, NE,
          PE, NE, PE, NE, PE, NE, PE, NE};
  end
  begin
    {H00, H01, H02, H03, H04, H05, H06, H07, H08, H09,
     H10, H11, H12, H13, H14, H15, H16, H17, H18, H19,
     H20, H21, H22, H23, H24, H25, H26, H27, H28, H29,
     H30, H31, H32, H33, H34, H35, H36, H37, H38, H39} <=
    {LD1, LD2, LD3, LD4,
     H00, H01, H02, H03, H04, H05, H06, H07, H08, H09,
     H10, H11, H12, H13, H14, H15, H16, H17, H18, H19,
     H20, H21, H22, H23, H24, H25, H26, H27, H28, H29,
     H30, H31, H32, H33, H34, H35, H36, H37, H38};
    x1<=LD0-LD1;
    x2<=LD1-LD2;
    x3<=LD2-LD3;
    x4<=LD3-LD4;
    y1<=LD1*LD1;
    y2<=LD2*LD2;
    y3<=LD3*LD3;
    y4<=LD4*LD4;
 
    SumS1<=SumS1-(SumS1>>3);
    SumS2<=SumS2-(SumS2>>3);
 
    LS1<=LevelS1-(LevelS1>>3);
    LS2<=LevelS2-(LevelS2>>3);
    CurTime<=CurTime+1;
  end
 
  begin
    z1<=x1*x1;
    z2<=x2*x2;
    z3<=x3*x3;
    z4<=x4*x4;
    yy1<=y1+y2;
    yy2<=y3+y4;
  end
 
  begin
    zz1<=z1+z2;
    zz2<=z3+z4;
    yyy<=yy1+yy2;
  end
 
  begin
    zzz<=zz1+zz2;
    SumS1<=SumS1+(yyy>>5);
  end
  begin
    SumS2<=SumS2+(zzz>>5);
  end
 
  begin
    if(SumS1>=LevelS1 && SumS2>=LevelS2)
    begin
      LevelS1<=LS1+(SumS1>>5);
      LevelS2<=LS2+(SumS2>>5);
      NadoT<=NadoT+3072;
    end
  end
end
always @(OutClock)
begin
  begin
    {CurShiftData, OutData}<=CurShiftData;
  end
  if(CurPos) CurPos<=CurPos-1'b1;
  else
  begin
    CurPos<=79;
    CurShiftData<=EndPos;
    if(EndPos==0 && EndPosSw)
    begin
      CurShiftData=TimeStep];
      EndPosSw=0;
    end
    else
    begin
      CurShiftData=RingData;
      EndPosSw=1;
      EndPos=EndPos+1'b1;
    end
  end
end
endmodule