What I did Wrong in my Verilog Project? (Quartus cannot compile it)

I found a construct in your code, that's absolutely not synthesizable. You can't built a counter without a clock (a posedge or negedge condition).

always @(LocData1)
begin
  if(DeMuxCounter)
  begin
    DeMuxCounter<=DeMuxCounter+1;

You should check, what you want to achieve here and find a clear synchronous construct for it. I also noticed ripple clocks in the design that may prevent timing closure.

You mentioned a input clock speed of 400 MHz. Do you mean that InReady is 400 MHz or 200 MHz?

I don't see at once an asynchronous read of RingData. I wonder, if it has to do with usage of blocking assignments. Altera RAM interference examples are exclusively using non-blocking assignments, according to it's synchronous function. Or you have removed the problem when simplyfying the code.

In any case, without forcing RAM inference for the large buffer structure, the design can't compile I fear.