What files are needed for GTL simulation in Modelsim?

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Quartus produces one .vo/.vho and one .sdo which cover all the timing corners.

For convenience, Quartus also produces a series of .vo/.vho for each specific corner.

You only need compile that .vo/.vho and it will load .sdo information for that corner.

You also need to compile your testbenches' HDL files.

You'll need the FPGA's cell library.

If the FPGA is Cyclone IV and you're using Verilog, then you need to load the cycloneiv_ver library.

You also need libraries for components that you use in your testbenches -- same as RTL simulation.

Ie, if one of your testbenches uses a DCFIFO or some other MegaFunction, then you need to load the altera_mf_ver library as well.

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Thanks very much, if I use .vo file which cover all the timing corners, how can I decide which corner I want to simulate?