what does tri1, tri0

That is one of the behavioral-only statements and I think it is not synthesizable.

You have to understand that Verilog was written oritinally as a netlisting language. Therefore they put in all kinds of structures that people put in chip design at the time and also looking a bit forwards. Digital logic using weak pull-ups was common in the 70's and 80's and it was to reduce the cost of the circuit by eliminating a lot of PMOS transistors. Today transistors are cheap, so this kind of design is restricted to just small niches.

Now, in synthesis world, you old build circuits that are very structured, use standard cells (ASIC) or FPGA LUTs. Then you would never have a weak pull-up. It is unpredictable what a synthesis tool will do with that. Will they consider it a wire, just give an error message, ignore it all together. There are synthesis tools that understand tri-state buffers to build tri-state busses but that is for ASICs, not for FPGAs.

Now, of course, to simulate in your behavioral testbench it is ok to do such things. So if you have a weak pull-up on your PCB, you can use tri, trireg, or perhaps a simple type "wire" and then use a PMOS component to connect it to supply1 and model your board in your testbench, but don't put these statements on anything that Quartus will be synthesizing..

Synthesis does some odd magic at times and often is not what makes sense, especially if you code devices like flops and latches not strictly how they should be written to make sure it properly converts the RTL to the structures you have. Check out http://www.altera.com/literature/hb/qts/qts_qii51007.pdf for proper coding rules on different components if you want to know more about this.