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Altera_Forum's avatar
Altera_Forum
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11 years ago

what does tri1, tri0

How tri1 and tri0 are implemented in quartus II. Can't understand results from synthesized code; module main3 (cols,LEDG,rows) ; // ------------ Port declarations --------- // input t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I'm not 100% sure, but I believe Quartus ignores pull up/down input attributes in Verilog.

You must set these I/O features in the pin assignment editor.

Then, the behaviour you observed makes sense, since those input pins are unbiased.