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Dolemy's avatar
Dolemy
Icon for New Contributor rankNew Contributor
2 years ago

What determines the maximum division factor of PLL in megawizard?

I am currently studying through the FPGA through Terasic DE2 I am using Quartus version 13.0spi. Recently, I learned how to divide or multiply CLK using PLL. I use Megawizard for this as it ...
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago
Hello,
Megawizard setting reflect hardware features, in this case of Cyclone II PLL. Review device manual to learn about PLL structure and setting range of pre- and postdivider. Cyclone II postdivider has e.g. range of 1..32. Since Cyclone III, divider range is larger, the new devices also implement a feature to cascade dividers. If you need slower clock, you can implement divider in FPGA fabric.

Regards,
Frank