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Altera_Forum
Honored Contributor
12 years agoBecause I discovered that HDLs don't like wire names starting with numbers, I added "p" letter in a front of all signals (and renamed 53clk to clk53 etc).
After I did these changes I checked - nothing changed in the simulation. Also I checked with older Quartus 9.0 - the same... Can attach the simulation with new names, but a bit later - away from my computer now (and again - it's absolutely identical to the simulation I already attached - except a slight change in signal names)...