Weirdest thing - MAX3000A simulation

If you review the gate level netlist (Technology Map Viewer), you'll notice that the design is implemented slightly different from the RTL, e.g. DD3-3 is clocked directly by p41. This explains some unexpected results in simulation.

Secondly you get warnings about hold time violations which can be related to the ripple clock topology.

There are possibly some oddities of the CPLD synthesis engine contributing to the problem, but essentially it's the bad design topology.