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Altera_Forum
Honored Contributor
12 years agoSorry I forgot to answer about possible timing issues - I don't think it's a problem here. The clock is the signal from external pin with 100 ns period - I'm pretty sure it's more than slow enough for this design/device.
I'm attaching the archive here. Unfortunately, I have not learned how to create testbenches yet - with this project I'm just overwriting the signal clk with 100 ns period... Thank you very much for spending your time on my problem !