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Altera_Forum's avatar
Altera_Forum
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12 years ago

Weirdest thing - MAX3000A simulation

I think I'm going crazy... I created a simple project for MAX3000A (schematic file, part of the schematic is attached) and tried to simulate in ModelSim - SE. https://www.alteraforum.com/forum/...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

You didn't answer the timescale question. In addition the "53clk" in your design is apparently a generated clock, the gate level netlist may look considerably different from the RTL.

Can you post a quartus archive of your design, including the testbench?