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In this case you'll inspect the RTL and gate level netlist and try to understand why the design is behaving as shown.
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Of course, I have looked at the design using netlist viewer . But the design is extremely simple – we are talking, basically, about one-bit counter that starts counting before the clock comes… I couldn’t see anything suspicious in the netlist. And changing the device to Max II (without changing schematics) eliminates this issue. Grounding counter’s reset instead of connecting it to the reset circuit helps as well, but, of course, in this case the logic is not working in the required way…
Unfortunately, I have to stick with MAX3000/7000 for several reasons. And I’m just starting, don’t have enough HDL knowledge to use it for the design – just need to re-create existing schematics using CPLD.
P.S. Thanks a lot to all replied !
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