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Altera_Forum's avatar
Altera_Forum
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12 years ago

Weirdest thing - MAX3000A simulation

I think I'm going crazy... I created a simple project for MAX3000A (schematic file, part of the schematic is attached) and tried to simulate in ModelSim - SE. https://www.alteraforum.com/forum/...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

O.K., a gate level simulation. In this case you'll inspect the RTL and gate level netlist and try to understand why the design is behaving as shown.

I know that Quartus CPLD synthesis hat some weaknesses in the past. MAX II in contrast uses FPGA synthesis tools.

A gate level simulation without time scale is meaningless, by the way. It might be a simple timing violation problem.