Weirdest thing - MAX3000A simulation

Gate level simulation is very slow. It has to compile the design into a netlist (a list of low level gates and registers) and then simulates that. An RTL simulation simulates the code directly, and runs much much faster. If you have altera schematics these need to be converted to HDL before RTL simulation can occur. This can be done via file -> conversion -> HDL file.

Be wary of this though, as you create two copies of the same thing. Forgetting to do a conversion when you update the schematic means the two are no longer matching. Much safer to have the whole design in an HDL (VHDL or Verilog).