Honored ContributorWhen running fitter I receive this warning:
Critical Warning: Input port inclk of PLL
"singlechannel:ch0_i|pll_enh:pll_enh_i|altpll:altpll_component|pll"
and its source clk (the output port of PLL
"singlechannel:ch0_i|pll_tx:pll_tx_i|altpll:altpll_component|pll")
have different specified frequencies, 19.4 MHz and 19.4 MHz respectively
Honored ContributorIs it a rounding error perhaps? Seems stupid to state that two clocks are inequal and not supply enough decimals...
Honored ContributorActually it may not be as stupid as you think if you think about why it may be occurring. However, I agree that it's not a very helpful message. But what it does do is indicate there is a problem somewhere. More than likely the constraints for the two clocks are being issued differently. For example, one constraint may be specifying the clock's period while the other is specifying clock's frequency in which case it probably is a rounding error. Open TimeQuest and look at the two contraints. You'll probably see rather quickly what's causing it.
