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Yes it's a valid circuit and asynchronous. The error can be expected in the other part of the design.
In terms of general FPGA design methodology, it would be reasonable to switch to a synchronous design, but it's not necessarily required. If the total design is asynchronous and doesn't latch data at the wrong time, it should manage to show the result on a 7-segment display.
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In practice, you cannot design proper projects in asynchronous logic in FPGAs. For student level miniature designs you may but and I see it wrong advise beginners to have their tiny circuit in asynchronous logic. If it was possible all the fuss about fmax would have disappeared and TimeQuest thrown in the bin.
The fpga design is based on rtl when a register exist on either side of logic cloud.
Moreover for testing you get cleaner waveforms when you are sampling your outputs at clock edge only away from delay effect.
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