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Altera_Forum
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12 years ago

Weird VHDL Multiplier Problem

Hello all, I was recently given reign over a DE0-Nano board by my research adviser to turn into a interference fringe counter of sorts but I am having some problems programming multiplication in V...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Yes it's a valid circuit and asynchronous. The error can be expected in the other part of the design.

In terms of general FPGA design methodology, it would be reasonable to switch to a synchronous design, but it's not necessarily required. If the total design is asynchronous and doesn't latch data at the wrong time, it should manage to show the result on a 7-segment display.